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Fast Evaluation of Transient Hot Spots in VLSI Chip Packages
Keywords: Transient hot spots, Power Blurring method, Thermal simulation
The reality of high temperature non-uniformity has become a serious concern in the CMOS VLSI industry limiting both the performance and the reliability of packaged chips. Thus the surface temperature profiles of VLSI ICs have been investigated in recent years. Thus far, thermal simulations have been limited to steady-state worst case conditions, which has caused the use of conservative margins in thermal designs. It is known that the worst-case peak power consumption and its corresponding peak temperature are rarely observed [1]. When the thermal budget is tight, this approach is too costly. The temperature non-uniformity evolves with time and so do the hot spots. The transient localized heating can cause timing errors or reliability failures. The state-of-the-art chip-level transient thermal simulation is such that the inclusion of any realistic package configuration is prohibitively too expensive to be done for physical design optimization or performance verification in the packaged environment. To drastically reduce the time for the chip-level thermal simulation, we developed a matrix convolution technique, called Power Blurring (PB). This PB method has its theoretical basis on the Green’s function method and the image blurring used in image processing. The PB method reduced the calculation time by three orders of magnitude compared to the Finite Element Analysis [2]. The PB method was further improved by applying the concept of the Method of Image. In this paper, we will demonstrate fast and accurate chip-level simulation of both steady-state and transient thermal profiles for packaged VLSI chips. This method is a good way to evaluate various packages depending on the performance and cost constraints. Our PB method yields accurate results with maximum error less than 3% for all case studies done and reduces the computation time by a factor of 100, compared to the simulations done by the industry standard tool, ANSYS. References: [1] Massoud Pedram and Shahin Nazarian, “Thermal Modeling, Analysis, and Management in VLSI Circuits: Principles and Methods,” Proceedings of the IEEE, Volume 94, Issue 8, Page(s):1487-1501, August 2006. [2] Travis Kemper, Yan Zhang, Zhixi Bian and Ali Shakouri, “Ultrafast Temperature Profile Calculation in IC Chips,” Proceedings of 12th International Workshop on Thermal investigations of ICs (THERMINIC), France, September 2006.
Je-Hyoung Park, Student
University of California at Santa Cruz
Santa Cruz, CA

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