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|Hybrid CSP Package: Challenges and Solutions in Design and Manufacturing|
|Keywords: Hybrid, 3D, High-density|
|The introduction of CSP hybrid package, where a wire bond die is stacked on a flip chip die, enabled the industry to integrate memory and ASICs in a smaller form and fit package compared to other 3D packages like stacked wirebond package or package-on-package. However, the process of making such a structure using conventional design rules and conventional processes like underfill (UF) and transfer mold limits the application to less complicated circuit interconnection with fewer I/Os, thus making it less appealing to the industry. This paper will discuss the challenges in making a high density Hybrid package and eventually the solution starting from design, such as substrate routing and bump design, to the assembly processes with detailed qualification and reliability test result.|
|Roden Topacio, Member of Technical Staff
MARKAM, ONTARIO L3R4S8,