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Low-k Interconnect Oriented Lead Free Sn-Cu Bump Process Integration with Sn/Cu Stack Plating
Keywords: SnCu, Stack plating, Low k material
We have demonstrated Low-k oriented lead free Sn-Cu bump process integration with Sn/Cu stack plating. The key features are lower cost process than Sn-Ag alloy plating with Sn/Cu stack plating and suitable for FC package with low-k interconnection with Sn-Cu material has high potential of stress alleviation effect. Fig.1 shows process flow sequence. Sn-Cu bump employed sequential Cu and Sn electroplating followed flux reflow. The reflow process carried out alloying Cu6Sn5 between Cu and Sn. The Cu6Sn5 layer placed at the bottom of Sn-Cu bump. We have found wide process latitude depended on stacked thickness ratio of Cu/Sn. The Cu concentration in Sn-Cu bump bulk region had not sensitive dependence on changing Cu/Sn thickness ratio. The ratio from 0.02 to 0.06, Cu concentration in Sn-Cu bump bulk region was saturated almost 0.7 wt%. The rest of Cu was moved to bottom and alloyed to Cu6Sn5. Therefore, over saturated concentration Cu was moved to bottom Cu6Sn5 layer. The concentration was controlled by changing Cu6Sn5 layer thickness at bump bottom as shown Fig.2 which was cross-sectional SEM photograph of Sn-Cu bump. The other hand, Ag concentration in Sn-Ag bump did not show saturation with bottom alloy layer. Therefore, it was difficult to control melting point because Ag concentration control was difficult. This is a one of advantage of SnCu bump. Each Single metal plating process with Cu and Sn stack has a cost advantage. Since the electrical standard potential difference between Sn and Ag is 0.938eV, the control of Ag concentration was difficult. In order to control Ag concentration, a lot of additives were including in plating solution with high cost. On the contrary, Cu and Sn single plating was easy, simple and low cost, in general. During thermal stress, SnAg bump consumed Ni from under bump metal, but SnCu bump did not. The High temperature stress test at 150C after 1000h showed SnCu did not consumed large number of Ni. Then the SnAg needs thick Ni under layer (typical 5um with plating), although Ni thickness under SnCu employed only 350nm with sputtering. Table 1 shows the results of TCT B (Thermal cycle test), PCT, HTS reliability test with low-k material interconnection, which use k=2.7 material. The Sn-Cu bump showed no fail even if 1000 cycle, although Sn-Ag bump showed all fail on pre-conditioning test before TCT test. Sn-Cu bump has a high creep rate. Therefore, Su-Cu deformed itself and alleviated the stress of thermal cycle for low-k interconnects. EM test also completed. As a conclusion, the Lead free SnCu bump system has a potential of most suitable candidate of low-k BEOL 65 nm and more shrinkage generation which has week mechanical property.
Tadashi Iijima,
Toshiba Corproation
Yokohama, Kanagawa 2358522,
Japan


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