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Estimation of Interconnect Models of SIP (System-in-Package) and POP (Package-on-Package) for IC-Package Co-Analysis and Optimization
Keywords: POP package, Interconnect Parasitics, Estimation
In this paper, we introduce a new, highly accurate, the parasitics estimation technique (PME: Package Model Estimator) of the 3D stacked package that can simultaneously consider both on-chip and off-chip parasitic effects at the early stage of chip design. The performance of the proposed technique was verified by application to a POP (Package on Package) designed for mass production. This paper mainly focuses on the estimation of electrical models of unrouted PCB traces in the early stage of 3D stacked package design by the use of the weighting factor (W) reflecting the irregular routability of a substrate design. The weighting factor as a critical factor of PME can be represented as the function of the routing angle () and the number of the crossover (C) between logical nets, which depend on the PCB substrate types being used. For the POP package design case, the errors in the PME method converge within a reliability range of 5% to the minimum boundary as well as the maximum boundary. It is clearly shown that the proposed estimation algorithm produces excellent results compared to the post-simulation models for simple as well as complicated POP package designs. The efficient chip-package co-design technique, which accounts for all necessary parasitic effects of the 3D stacked package, can accurately predict the upper and lower boundaries of the noise margin for worst cases. Therefore, as a good solution for chip-package co-design, the preliminary package model estimator can successfully estimate the lumped circuit model of normal substrate packages as well as advanced packages such as POP, simulate the SSN noise in the early co-design stage by chip and package designers, who can avoid making timing consuming design iterations in the later design stages, and ensure quality manufacturing at lower cost.
Eunseok Song, Signal Integrity Engineer
Samsung Electronics
Yongin, Gyounggi 446-711,
Korea


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