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Bend Testing Direct Chip Attach Bump Architectures with Stress Mode Correlated to Field-Wearout in Handheld Applications
Keywords: Chip Scale Package, Four-Point Bend Testing, Bump Architecture
Our previous work demonstrated a field wearout mechanism in direct-chip-attach Chip Scale Package (CSP) electronic assemblies correlated to low-strain, high cycle multiaxial stresses associated with PC board bending. This multiaxial stress mechanism is not activated by traditional thermal cycling tests, but can be reproduced by subjecting test boards to high cycle deflection with a custom test fixture. We dub our custom test apparatus “MultiFlexer”, designed to rapidly stress daisy chain test boards thus providing rapid and low-cost feedback on possible new bump-attachment architectures. We show example bending performance from single- and multi-layer BCB, and polymer-collar-based bump architectures. Clearly superior lifetime performance of the single BCB polymer collar design is made more apparent by the fact that the polymer collar devices did not exhibit a through-solder failure mechanism, but even outlasted the flexible multilayer build-up PC board they were mounted upon. Introduction: Our prior work utilized board bending approaches to augment classical temperature cycling in order to examine the relative durability of various CSP process architectures. This paper represents the last of our efforts to characterize differences between architectures that place compliant polymers between the bump and silicon (“narrow via”), versus UBM placed directly over the chip passivation (“wide via”) versus the polymer collar developed by Flip Chip International.
Mark R. Larsen, Equipment Engineer
Fairchild Semiconductor
West Jordan, UT
USA


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