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Reliability Improvement of Resin Stress Buffer Layer Type Wafer Level Chip Size Package for Automotive Applications
Keywords: wafer level package, reliability, simulation
With expanding applications of portable electronic devices such as mobile phones, packaging technologies that enable make it small, slim and high density have been evolved at rapid speed. In these technologies W-CSP (Wafer level Chip Size Package) is developed as an ultimate package that enables a real chip size package, and its usage in such fields has been increasing during last years. Recently, in accordance with increasing the requests of small package on car electronic devices, the adoption of W-CSP has been increasing at the car electronics field. Thermal cycle reliability at a board level test is important all the more. Compared with interposer type CSP, W-CSP is simple structure that is formed on IC chip. In other words, it is difficult to make complex structure on W-CSP. Therefore structure design to decrease thermal mechanical stress caused by differences in thermal expansion between the IC chip and the substrate is very important to obtain enough thermal cycle reliability for board level test. In addition, it is important to figure out influence of the dimension, material properties, and so on. In this paper, we describe the development of a W-CSP structure that includes a resin stress buffer layer to improve thermal cycle reliability on a board level test using finite element method. Applying finite element method results, the modified W-CSP reliability has improved more than double compared with an ordinary W-CSP reliability at a thermal cycle board level test.
Shunpei Ogaya,
Seiko Epson Corporation
Fujimimachi, Suwa-gun, Nagano 399-0295,

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