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Understanding Power Integrity in System Designs
Keywords: Power Integrity, Power delivery, co-design
Designing optimal power supply scheme for high speed digital systems has become a great challenge in recent years as designs move towards low voltage systems with high current capacity and high data rates. The fundamental problem that designers face today is how to efficiently provide sufficient and stable power supply to core circuitry and IOs on chips through printed circuit boards (PCBs) and packages. To achieve such design goal in low voltage systems, low impedance path has to be designed and implemented on the entire power delivery network, i.e. power consumption over packages and PCBs needs to be minimized and controlled within design budget. This paper first discusses the three important aspects of Power Integrity (PI), sufficiency, efficiency, and stability. It emphasizes that IC designers need to be aware that a low power device will not work properly if power consumption on package and board is not carefully analyzed and managed. The paper then presents how power delivery system (PDS) should be designed, modeled, analyzed, and verified using IC/package/board co-design methodologies. Finally, it demonstrates co-design and co-simulation flows of package-aware IC power design, chip-aware package/board power design, and system power delivery validation. With the presented flows, designers are able to identify power delivery problems and correct them by modifying chip, package, or board designs to achieve sufficient, efficient, and stable power supply in low voltage systems.
Zhen Mu,
Cadence Design Systems Inc.
Chelmsford, MA
USA


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