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RF MEMS Flip-Chip Package Design: Finite Element Modeling and Experimental Verification
Keywords: Flip-Chip Package, Finite Element Modeling , RF MEMS
RF MEMS device performance can be very sensitive to the die deformation, so appropriate methods need to be considered for the design of the device and package. A numerical approach is developed to study the die deformation due to the thermal mismatch between die and package substrate that is driven, in part, by the multiple metal-oxide layers associated with the integration of HV RF-CMOS and RF MEMS device layers. The numerical approach consists of two steps: die-level modeling and package-level modeling where the die is flipchipped on a ceramic substrate. The die dimensions (3.3mmx3.7mmx0.2mm) and substrate dimensions (5.2mmx5.2mmx0.4mm) are much larger than the scale of the MEMS device or the underlying metalization. The experimental verification is completed by comparison of both die-level and package-level models to measurements using Twyman/Green (T/G) interferometry. We have found die warpage from modeling to be in good agreement with that of T/G interferometry measurement from -40 C to 210 C. The warpage of an unassembled die is approximately 0.3um at room temperature and varies non-linearly as temperature changes. The non-linearity is attributed to the plastic deformation of metal in the multiple metal-oxide layers. In the die-level modeling, composite elements are used to represent 15 thin metal-oxide layers with a total thickness of approximately 20um on the die. It is demonstrated that the accurate multilayer construction is critical to capture the non-linearity of die warpage over temperatures. The validated die-level model is then transferred to package-level model to study the behavior of the die assembled on the package substrate. The warpage of the die assembled on the package is approximately 1.1um at room temperature and changes more linearly as a function of temperature, which implies package plays a significant role on die deformation. To optimize the package design, a parametric study is conducted with the verified package-level model to understand the die deformation as a function of die thickness, substrate thickness, and standoff height of solder joints.
Li Sun, MEMS Packaging Engineer
WiSpry, Inc.
Irvine, CA

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