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Bump on Flexible Lead for Wafer Level Packaging
Keywords: bump, flexible, Wafer Level Package
A chip-to-substrate interconnect technology is introduced which uses flexible structures to accommodate the CTE mismatch between a chip and a PWB substrate and hence is reliable without underfill. Increased flexibility of the bumps can lead to an increase in the reliability of large Flip Chips. To achieve a high flexibility, the lead-free bump is located on a flexible lead. The flexible lead consists of a copper line embedded in a polymer-bridge which is located on an air-gap. For a small bump height, which is necessary to achieve a small package height, the stress due to CTE mismatch is then absorbed in the flexible lead. FEM simulations are performed to find out the optimum shape of the leads. Prototype chips have been designed and fabricated using wafer level packaging processing methods, as photolithography, electroplating and wet-etching. The process flow and assembly of the flexible interconnects without underfill are presented and discussed.
I. Eidner,
Fraunhofer Institute for Reliability and Microintegration
Berlin 13355,
Germany


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