Here is the abstract you requested from the IMAPS_2008b technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.
|Wafer Level Packaging: Balancing Device Requirements and Materials Properties|
|Keywords: Wafer Level Bonding, 3D Packaging, Device Integration|
|Wafer level packaging for MEMS devices in the front end has a field proven history that now allows for these techniques to facilitate back end packaging and device integration. The most common methods for MEMS assembly include anodic and glass frit bonding which comprise more than 70-80% of all volume manufacturing processing today. However, metal based bonding schemes such as metal eutectics and metal diffusion seals provide increased hermeticity levels and facilitate inter-wafer and intra-device electrical connections. Adhesive bonds using a variety of materials types has been a long standing method for die to package assembly and over the past several years these techniques have been merged with metal techniques to enable wafer level 3D packaging. At the same time that decisions are made regarding the choice of bonding methods it is necessary to consider the upstream and downstream processing. Integral to the success of the total packaging flow is balancing the thermal expansion issues of the various layers and substrates to minimize wafer bow and device stress. As an example, the bonding of compound semiconductor devices to silicon for optoelectronic devices often leads to excessive bowing of the wafers that prevents further lithography steps and uniform backthinning operations. In addition to controlling the maximum bond temperature, the heating and cooling rates during bonding play an equally important role. Figure 1 shows the influence of cooling rate on dislocation formation in GaAs bonded to Si. The scanning acoustic microscope images are able to reveal subsurface cracks that result from the thermal stress associated with difference expansion rates during cooling. This paper will focus on new methods used in wafer level packaging for next generation products such as CMOS Image sensors and stacked systems. Figure 1. Sonoscan images of GaAs to Si taken after bonding. The effect of cooling rate on the formation of microcracks is apparent by comparing the slow cooling at 1C/min on the left to the 1.5C/min and 2C/min results to the right.|
|Shari Farrens, Chief Scientist - Wafer Bonder Division
Waterbury Center, VT