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Thermosonic Gold Stud Bump Attach for Large ICs on Laminate Substrates
Keywords: Flip-chip, Stud bump, Interconnect
Miniaturization and reliability are the two most critical aspects when designing packaging for a medical implantable electronic device. As sizes of implantable devices shrink, some of the more mature packaging methods such as wire bonding become less feasible due to the additional layout area that is required. A flip chip package that employs gold stud bump interconnects is a proven alternative to both chip/wire assembly and flip chips that rely on wafer-level bump redistribution. Gold stud bumping offers several advantages over wafer-level bumping, such as increased flexibility and cost-effectiveness for prototype and small run environments. This assembly methodology consists of three primary steps: 1) Bumping of the silicon IC using common wire bonding equipment. 2) Connection of the bumped IC directly to the substrate by Au-Au bonding. 3) Underfilling the IC after attach for increased reliability. This type of interconnect is common for small devices with low I/O counts, but newer models of flip chip placement equipment are pushing the longstanding limitations of this process. This paper discusses the development and testing of a thermosonic gold stud bump attach process for a large silicon IC (7.5 x 11 mm with 102 I/Os) to an organic laminate PCB.
Ian Hardy, Process Engineer
Crane Electronics
Redmone, WA

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