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|An Experimental and Computational Study of the Current Carrying Capacity of High Performance PWB Interconnections|
|Keywords: Conductive adhesive paste, Via Current carrying capacity, Power|
|Recent technology advancement has enabled enhancement in PWB electrical performance and wiring density. These innovations have taken the form of improved materials, novel PWB interconnect structures, and manufacturing technology. One such advancement is Z-axis conductive interconnect. The Z-interconnect technology involves building mini-substrates of 2 or 3 layers each, then assembling several mini-substrates together using conductive paste. Designing and manufacturing the mini-substrates separately, then assembling them together, makes it possible to reliably manufacture substrates with no via stubs, very low-loss materials, and high wiring density. The conductive paste is not quite identical to copper, its conductivity is a bit lower and structurally its different than a plated copper barrel. This paper will examine some thermal and mechanical performance metrics to compare vias with and without conductive paste joints. In most high performance systems (with the exception of board cooled applications such as in the avionics industry), the bulk of the power is dissipated in the chip package with the PWB playing a minor role. However, power delivery is a primary function of the PWB. Increased power requirement translates to increased electrical current flow in the board which leads to ohmic (joule) heating of the conductors. Thus, the current carrying capacity of conducting layers, joining layers, planes, and vias become important from both a performance and reliability standpoint. Traditional industry standard guidelines have tended to focus on generic conditions and conservative analysis. While adherence to these guidelines is sure to meet performance requirements, there are many situations where better optimized designs are needed. Consequently, an application oriented approach is better suited is preferable. This paper deals with the current carrying capacity of Z-interconnect vias and joining layers under specific, commonly encountered conditions. Both laboratory experiments and simulations are used to perform the study. An experimental test vehicle has been used to characterize temperature rise of PWB vias under different conditions. A numerical model is developed and validated with the experiment data. The numerical model is then exercised to determine internal via temperature rise under a variety of conditions. Results obtained so far indicate that these joints are capable carrying currents in range of 3A to 5A or higher. Originally sent to Advanced Packaging session.|
|Michael Rowlands, Senior R&D Electrical Engineer