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Trade-off Between Speed and Defect Tolerance of QCA Designs in the Presence of Different Manufacturing Defects
Keywords: quantum dot, QCA circuits, speed and defect tolerance
Quantum-Dot Cellular Automata (QCA) is one of the most promising nanotechnologies that advance the current CMOS VLSI technology to a new era. In our earlier work, it was found out that the third level of design hierarchy that is Place and Route (P&R) stage holds the key for resolving design for performance issue in case of various QCA circuits. However, to operate at room temperature, the diameter of a quantum-dot must be reduced to approximately 10 nanometers. Such a nano-scale design requirement poses great challenge in manufacturing QCA systems. There are several manufacturing processes for QCA systems, among those, self assembling monolayer (SAM) has gained the most popularity. Within SAM, depending on the choices of molecules, the manufacturing processes vary, which in turn make the QCA systems prone to different types of defects some extent. As the chance of occurrence of different defects varies from one manufacturing process to another, the intention in this work is to see how optimized QCA designs perform in the presence of these manufacturing defects, i.e., to find the tolerance level of the QCA designs where clock zones have been optimized for speed. The traditional QCA design has been compared with the optimized (in terms of clock zone) QCA design in the presence of three different types of manufacturing defects namely cell omission, cell displacement, and cell misalignment. It has been observed that when cell omission defect is more likely, traditional QCA designs are more robust compared to the faster ones. However, cell displacement defect near the output cell has the same effect on traditional and faster QCA designs. In this paper, the trade-off between speed & defect tolerance will be explained for QCA designs in the light of different manufacturing processes.
Satyaki Ganguly, Student
Temple University
Philadelphia, PA

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