Here is the abstract you requested from the IMAPS_2008 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.
|Overcoming Challenges in Thermally Enhanced BGA Packaging with Low-k Silicon|
|Keywords: low-k, thermally enhanced PBGA, reliability|
|All market segments continue to put cost pressure on semiconductor and packaging suppliers in order to stay competitive. Reducing silicon area while providing more silicon functionalities increases potential die count per wafer and lowers the die cost. Staying in wire bond packaging instead of migrating to flip chip packaging further provides a cost competitive advantage. Wire bond packaging for silicon devices has been the backbone of the semiconductor industry to serve communications and networking customers for many years. Innovative interconnect routing and IC design and fine pitch wire bonding capability enable silicon to have 900 bonding pads in an area of 60mm2. The high wire count and wire density is unprecedented in thermally enhanced plastic ball grid array (PBGA) packages with an internal heat spreader, which is commonly denoted as TE-PBGA-II. With the further shrink of the silicon dimension, the low-k inter-layer dielectric (ILD) material has been widely used to replace the traditional SiO2 ILD in order to reduce the interconnect delay. Low-k dielectric by definition has a dielectric value of less than 3. The introduction of low-k ILD material into silicon imposes new challenges for high wire density packaging. In particular, the inherently weak adhesion in the low-k interconnect makes the silicon more susceptible to a failure mode called ILD crack or delamination that causes electrical failure during temperature cycling test. This paper will discuss the challenges and resolution during the packaging development for low-k products with high wire density in large 31x31 and 35x35mm TE-PBGA-II packages. Challenges range from wafer dicing through difficult test structures in the scribe streets, die attach fillet height control, wire bonding on low-k bond pads, and molding low-k silicon in a large package. Weibull calculation was also performed to map the temperature cycling durations to end user’s operating conditions in order to ensure the product quality in the specified customer environment. Alternative methods including Finite Element Modeling and extended package reliability testing were used to demonstrate the robustness of the low-k packaging solution.|
|Tu Anh Tran, Engineering Manager
Freescale Semiconductor, Inc.