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Thermal Simulations for 4-Layer Stacked IC Packages
Keywords: thermal simulation, 3D stcaked IC package, hot spot
Since the shortened wiring length between devices and chips in stacked IC package can reduce the signal delayed effects and improve many electrical characteristics, the topics of stacked IC package are now being studied extensively. Although the electrical benefits are greatly increasing in stacked IC packages, their corresponding thermo-mechanical problems are raising as well, including the problems of heat dissipation, induced stresses, interfacial delamination, via cracking and so on. These problems always cause failures or fatigues in stacked IC packages and become critical reliability issues. In order to obtain thermal distributions in stacked IC packages, the 4-layer stacked IC package (chip on chip) with TSV (through silicon vias) structure has been constructed as our test vehicle in this paper. Not only the temperature distributions but also the junction temperature and thermal resistances in 4-layer stacked IC package have been obtained. In addition, the hot spot effects induced non-uniform temperature distributions in the same structure have also been illustrated. Further, for the purpose of studying the sensitivities of isotropic and anisotropic thermal conductivity of underfill, the factorial design methodology has been adopted. These results will be useful design guidelines to engineers when optimum thermal solutions in 4-layer stacked IC package are demanded.
Chih-Kuang Yu, Design Engineer
EOL/Industrial Technology Research Institute
Chutung, Hsinchu, 310,
Taiwan


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