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Alternative Processing Methods for Copper Through Silicon Vias
Keywords: 3D packaging, Through Silicon Vias, copper plating
Over the past decade, there has been significant development of 3D packaging due to its reduced interconnect length and associated parasitics. Through Silicon Via technology (TSV) enables short and dense interconnects with increased speed and reduced noise. Via-first and Via-last are the two ways of fabricating TSVs based on the order of forming vias. The Via-first way of fabricating TSVs, before fabricating devices, includes blind via formation, deposition of seed and barrier layers, and copper plating followed by device fabrication. The process wafer is then attached to a carrier for back grinding and backside processing. In the Via-last approach, wafers with devices are processed to form blind vias, which are then plated before the wafer is attached to a carrier. Then the backside is thinned and additional metal applied. The Via-last approach has been followed by industries that are post-processing device wafers for 3D applications. At the University of Arkansas, most of the research projects have been based on the Via-last approach of fabricating TSVs. The method reported here is a novel Via-first approach of bottom-up filling of through vias using copper DC plating. Blind vias of aspect ratio 6:1 are etched with Bosch scallops in a high resistance process wafer. This method involves two carrier wafers. The first carrier is bonded to the process wafer with a double-sided thermal release tape, which provides mechanical support during thinning. The process wafer is thinned down to 200 m by grinding and blanket etch in RIE, until the backside of the vias are exposed. The process wafer is then debonded. The second carrier has a Ti/Cu/Ti seed layer to initiate copper plating and is bonded using Brewer HT-250 thermoplastic, a high temperature adhesive. The adhesive under the vias is etched away to expose metal on the carrier for plating. Copper is plated using DC current on titanium for shearing of plated vias from the carrier wafer. Scallops inside the vias provide mechanical support to the plated copper. Wafers are then debonded at 250C and tested. Process wafers undergo CMP for planarization, and then would be processed for devices.
Gayathri Devi Jampana, Graduate Research Assistant
University of Arkansas
Fayetteville, AR
USA


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