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3-D VLSI Structure for High Power and High Speed Computation
Keywords: 3-D VLSI, TSV, Cooling
The University of Arkansas has performed extensive research on a novel 3-D packaging technology by die stacking. This method has the potential to address the cumulative yield problem of 3-D stacking and is designed to handle high heat flux and provide high speed interconnections. TSVs filled with copper are manufacutred by DRIE and reverse pulse plating to provide signal paths between active devices and the back side of individual layers. Copper posts and dams capped with tin are plated on the back side of most layers. After preselecting known good dies, copper posts and dams are joined to the matching pads on adjacent layers by copper/tin intermetallic. Vertical electrical connections are realized by posts and vias. Mechanical support is provided by both copper dams and posts. Microfluid channels are formed by each pair of die layers and dams in between. Coolant is circulated in the channels to remove 20 W heat from each layer. The thermal test vehicle comprises four TSV die layers. Three of them have posts and dams for interlayer interconnection. Thin film heat dissipation resistors are placed in each layer to simulate device power dissipation. Resistive temperature sensors are also embedded in every layer to monitor the performance of the cooling mechanism. Daisy chains are also included for reliability test. Up-to-date experimental results will be presented in this paper and at the conference. Design rules based on these results will also be discussed.
Yang Liu, Student
University of Arkansas, HiDEC / ENRC
Fayetteville, AR

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