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Optimization of Redistributed Layers between Heterogeneous Devices for Wafer-Level Integration
Keywords: pseudo-SOC, wafer-level integration, chip-redistribution
The authors have developed a pseudo-SOC technology by applying the chip redistribution in wafer with inter-chip resin incorporating heterogeneous chips, and redistributed layer with the most advanced semiconductor processes [1]. In the previous researches, the authors have studied on the optimization for the mechanical stability of pseudo-SOC device through the stress analysis and the fabrication of a pseudo-SOC device with RF-IC and passive components integrated. Although the integration density was 16 times higher than that of SIP, the line/space of the redistributed layer was 50um/50um, same as that of SIP. In this research, the authors focused on the improvement in the pitch of the redistributed layer by improving the planarization and the adhesivity of the underlying layer. Key points were described below.Planarization between integrated devices and the inter-chip resin was improved by improving the chip redistribution process using device transfer method and vacuum printing method. By inserting polyimide insulation layer as planar layer, it was improved further. Finally the step between the integrated devices and the inter-chip resin decreased to less than 2um. Insertion of the planar layer also increased the adhesivity between the redistributed layer and the inter-chip resin by covering the resin surface. Plasma treatment was carried out before the formation of the planar layer and the redistributed layer for improving the adhesivity further. As a result, redistributed layer with fine pitch of 15um/15um in line/space was achieved without being peeled off in the process. Thus, the redistributed layer with a pitch 3 times finer than that of the device previously developed was realized, leading to the miniaturization of the device. [1] Y. Onozuka et al.,
Yutaka Onozuka , Research Scientist
Toshiba Corporation
Kawasaki, Kanagawa 212-8582,
Japan


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