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Formation of Through-Silicon-Vias using Sn Filling Process for 3D Packaging
Keywords: chip stack package, through silicon via, Sn via
Through-silicon-vias were formed with Sn filling process and their characteristics were evaluated to form three-dimensional-interconnection structure of chip stack packages. Contrary to the conventional Cu vias which require complicated Cu electroplating process, Sn vias could be formed easily by Sn electroplating and reflow. Sn via filling behavior did not depend on the shape of Sn electroplated layer, allowing much wider process window for Sn via formation compared to the conventional Cu via process. Interlocking-bumping structure was formed by inserting Cu bumps of 20 diameter into Sn vias of 50 diameter at 250 for 2 min. Melt-joining-bumping structure was formed by reflowing Sn bumps of 55 diameter on Sn vias of 50 diameter at 250 for 2 min. Both interlocking-bumping structure and melt-joining-bumping structure exhibited chip shear forces much higher than those of the planar Cu via/bump structure. Comparing microstructures of the interlocking-bumping structure and the melt-joining-bumping structure with the conventional planar Cu via/bump interface, it is expected that much higher mechanical reliability can be obtained for the interlocking bump structure and the melt-joining-bumping structure formed on Sn vias.
Tae-Sung Oh, Professor
Hongik University
Seoul 121-791,
Korea


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