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A Low Power 5.5 GHz Current Reuse LNA for Wireless LAN Receiver
Keywords: Low noise amplifier, current-reused LNA, Receiver Front-End
This paper presents a fully integrated CMOS LNA with on-chip spiral inductors in 0.18m CMOS technology for 5.5-GHz unlicensed national information infrastructure (U-NII), 802.11a and IEEE 802.11n wireless LAN Receiver. By using a cascode current reuse structure with inter-stage inductors we achieved low power consumption and high power gain. We proof that the inter-stage inductors must be designed with a new method compared to newly published papers. This structure is based on two cascode configuration to provide a good output swing thus allowing the integration in low voltage technology. This configuration also permits good input impedance matching, low noise figure and high reverse isolation. Complete simulations of the circuit at 5.5-GHz, center frequency, have shown that the circuit has 3.1dB NF, 1.2GHz 3dB power bandwidth, 20.63dB power gain (S21), high reverse isolation (S12)<-45dB, -29.4dB input matching (S11), -25dB output matching (S22), and -15.9dBm 3th order input intercept point (IIP3). The power consumption is 3mW at 1.8V supply voltage. The circuit shows high power gain and high reverse isolation. Power consumption and noise figure are quite low compared to other published works. The LNA has good power gain, lower power dissipation, low noise figure, increased reverse isolation, increased 3dB power bandwidth, and it can be designed to meet the requirements of input/output impedance matching at both frequency bands. These are achieved by employing a current reuse structure for LNA and iteratively designing the inter-stage inductors. Also the simulation results confirmed the design steps for the inter-stage inductors.
S. Toofan, Ph.D. Student
Iran University of Science and Technology , Politecnico Di Torino
Tehran 16846,

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