Here is the abstract you requested from the rf_2008 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.
|High-Efficiency Class-F Amplifier Design with Stacked Stab Structure in Multi-layer Package|
|Keywords: class-F amplifier, stab impedancematching design, multilayer package|
|High-efficiency class-F power amplifier design with multi-layer stab matching circuits has been investigated. Harmonic load-pull simulation until 9-order harmonic frequency indicates the compact impedance-matching stab structure for a load of the high efficiency amplifier. The radio frequency class-F amplifier has been theoretically predicted to have 100-% efficiency by means of its load impedance such as short for even harmonic frequencies, open for odds. However, in fact it is hard to realize such a high efficiency. The impedance matching design for high-order harmonics and compact implementation of the complex matching circuits are key points. The micro-strip-line 1/4-wavelength stab structure is effective for the matched load impedance. When the impedance of microstrip stab lines is designed to match for frequency raging from low- to high-order harmonics, the high efficiency cannot be achieved as far as using 1 layer, nor area of matching circuits is shrunk. In this work, multi-layer structure involving both stab layers and vias is proposed and designed. Several 1/4-wavelength microstrip-line stabs in each layer correspond to optimal matching load for several harmonic frequencies, then each layer is stacked and connected with interlayer vias. For high-efficiency operation, the widths, lengths of stab and via, and total load impedance of them are simulated and discussed with load-pull characteristics at until 9-order harmonics. The measured parameters of fabricated RF-CMOS amplifiers are used for power efficiency evaluation. Simulation results show that class-F CMOS amplifier with the multilayer designed stab/via load is a candidate for GHz-band high-efficiency power amplifier.|
|Michio Yokoyama, Associate Professor
Yonezawa, Yamagata 992-8510,