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3D Wafer-Scale Integration for RF and Digital Applications
Keywords: Wafer Scale Integration, Heterogeneous Integration, Wafer-Level Packaging
Northrop Grumman Space Technology has developed an integration technology that is capable of intimately integrating III-V semiconductor devices with Si CMOS under DARPA’s COSMOS program. The integration approach is based on a direct face-to-face bonding between pre-fabricated III-V chiplets and CMOS wafers. It is capable of integrating CS (compound semiconductor) devices from smaller wafer substrates to a larger Si host wafer as well as integrating multiple CS technologies onto the same Si CMOS host wafer. This process can be applied to virtually any CS and Si technologies. Figure 1(a) shows the main steps of the AHI (Advanced Heterogeneous Integration) approach: Chiplet singulation, chiplet transfer and chiplet bonding. Figure 1(b) is the simplified flow diagram of the AHI process. Figure 2(a) is a cross-sectional presentation of an integrated CS/CMOS circuit and Figure 2(b) is a SEM photograph of the fabricated circuit, showing the InP chiplet on a silicon substrate. Integrated differential amplifiers (DAs) have been demonstrated using this 3D AHI integration approach. Figure 3 presents the data obtained from one of the integrated DAs. This DA demonstration integrates the 0.18um Silicon CMOS technology with 6 layers of interconnections from Jazz Semiconductor and NGST’s 0.4um emitter high speed HBT technology. Further integration details on AHI as well as demonstrated integrated circuit data will be presented in the full paper.
Patty Chang-Chien,
Northrop Grumman Space Technology
Redondo Beach, CA

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