Abstract Preview

Here is the abstract you requested from the Thermal_2008 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.

Thermo-Mechanical Design Challenges in Validation Platforms
Keywords: cooling, temperature margining, Vaidation platforms
Some of the parameters of the semiconductor industry that have grown exponentially over the past three decades include chip complexity, chip performance, feature size and the number of transistors produced each year. As silicon technology continues to scale per Moore’s law, multi-core and many-core are the new trends of the semiconductor industry. Accordingly, Intel is transitioning to silicon architectures with multi/many cores on the die to provide increasingly higher performance in contrast to the past trends of achieving the same results with larger monolithic cores. As the transistor-count and core-frequency increase with every generation of microprocessor, the current consumption has been growing at an exponential rate. Furthermore, the thermal design power (TDP) of the microprocessors has been increasing due to ongoing added new features into the design of microprocessors. These added features and functionalities have created thermo-mechanical design challenges primarily because of limited keep-out-volume (KOV) available for cooling solutions due to compact placement of the components on the motherboard to support higher bus-speeds. The validation platforms designed to validate Intel’s microprocessors and chipsets have even greater thermo-mechanical challenges due many unique requirements of such platforms. These requirements include ease of accessibility, compatibility with Logic Analyzer Interfaces (LAIs), need for thermal margining (from 0°C to 100°C) tools (TT) and need for backside probing and hot swapping. Furthermore, the thermo-mechanical challenges for validation platforms continue to grow as there is increasingly need for sockets for all packages that require stepping changes. Unlike in a standard enabled OEM system where chipset packages are soldered down, Intel’s validation platforms require sockets for chipset packages to allow ease of replacement of these devices into the mother-board as successive steppings become available. The requirements for sockets, nominal cooling thermal solutions, temperature margining tools and limited KOV on the mother-board create significant challenges in designing mechanical retention mechanism for sockets and thermal designs. In this paper, we present an innovative methodology of active air cooling coupled with mechanical retention designs that meet all of validation platform’s requirements. In addition, we present the design methodology of peltier-based temperature margining thermal tools. Both these solutions are compatible with the soldered-down as well as socketed packages. Some illustrations of these methodologies are shown in Figures below. These methodologies can serve as Best Known Methods (BKMs) for delivering novel designs for nominal cooling and temperature margining thermal tools to address the small factor, dense pad-pitch, high pin-count and high TDP challenges of Intel’s validation platforms.
Rahima K. Mohammed, Engineering Manager
Intel Corporation
Santa Clara, CA

  • Amkor
  • ASE
  • Canon
  • EMD Performance Materials
  • Honeywell
  • Indium
  • Kester
  • Kyocera America
  • Master Bond
  • Micro Systems Technologies
  • MRSI
  • Palomar
  • Plexus
  • Promex
  • Qualcomm
  • Quik-Pak
  • Raytheon
  • Specialty Coating Systems