Abstract Preview

Here is the abstract you requested from the Thermal_2008 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.

Enabling Dynamic Voltage & Frequency Scaling In Next-GenerationMicroprocessors: Thermal & Reliability Considerations
Keywords: dynamic, scaling, thermal reliability
In the high performance computing arena, the use of multi-core processors which support hardware threading is becoming more common. These advanced microprocessors are used in high end servers which perform intensive data manipulation, graphical visualization and floating point computations. To be able to support this demand for performance, each advancing generation of microprocessors features smaller transistor gate lengths than the preceding ones. As such, the semiconductor industry has moved from 130 nm process technology (circa 2000) to 65 nm technology (available today) and is moving towards the 45 and 32 nm technology (anticipated 2009 to 2010). As the transistor technology evolves and gate lithography shrinks, microprocessor power has continued to rise, and in particular the contribution of static leakage power to the total chip power continues to grow. Since the dynamic power (ie switching power) dissipated by a silicon chip is proportional to the square of the supply voltage and the frequency, a common theme to manage power in high end applications is through Dynamic Voltage and Frequency Scaling, or DVFS. In the course of normal die operation, the heat transferred from the chip to the ambient manifests in a temperature field in the cooling solution, and also in the hardware attached to the cooling solution- the package on which the chip is attached, the boards to which the chip package is attached, the electrical interconnect (socket) and so on. As is to be expected, with a DVFS policy in place the temperatures of the solder joints in the connector/socket are likely to be influenced; and the fluctuating temperatures are likely to cause aging of the solder joints, reduced connector life and ultimately the failure of the interconnect. As such, it is important to study the interaction of DVFS with overall connector reliability. To this end, in this study we focus on a sample application where a CPU module containing a thermal test vehicle is subjected to controlled laboratory thermal testing. The resulting temperature data are used in system identification studies to obtain linear, causal time-invariant models for the thermal behavior of the CPU junction, heatsink and connector temperatures as a function of dynamic power load. Chip temperature was sensed by a thermal diode, while all other temperatures were measured by thermocouples. Response to cyclic heat generation in the chip produced a frequency-dependent response at each temperature measurement location. The Bode plots for these models can be readily used to identify the frequency ranges of power fluctuation for which the chip, heatsink and connector temperatures are largely uninfluenced. Equivalently, the results of this study can also be used to identify power fluctuation frequencies which cause harmful temperature field fluctuations that in turn compromise solder joint reliability. Using this unified framework based on system identification provides the thermal engineer a valuable means to provide feedback to the chip design teams regarding the impact of power fluctuations, and helps recommend to the chip design teams 'thermally acceptable' ranges of power fluctuation frequencies to be used in conjunction with a DVFS policy.
Sai Ankireddi, Staff Engineer
Sun Microsystems Inc.
Santa Clara, CA

  • Amkor
  • ASE
  • Canon
  • EMD Performance Materials
  • Honeywell
  • Indium
  • Kester
  • Kyocera America
  • Master Bond
  • Micro Systems Technologies
  • MRSI
  • Palomar
  • Plexus
  • Promex
  • Qualcomm
  • Quik-Pak
  • Raytheon
  • Specialty Coating Systems