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PowerRibbon – An Alternative Power Interconnect for Hybrid DC-DC Converter Multi-Chip Packages
Keywords: PowerRibbon, DC-DC Converter, Multi-Chip Package
DC-DC converters are important power management systems. Such systems are typically built with several individual packages, a driver and two specific MOSFET devices. Over the years, significant power efficiency improvements have been achieved with such discrete designs. Space and cost reductions were achieved by a migration to smaller packages, for example from DPAK to SO-8, and later to Power QFN packages. Recently, PowerRibbonâ bonding was adopted as an effective power interconnect in small discrete power packages. The technology creates massive interconnects that fit into small and thin packages, offering an attractive combination of high electrical performance and reliability at low cost. But ever more efficient, more compact and cheaper power management solutions are required. Especially where current and load transient requirements are increasing, for example in notebook and server applications, operating frequencies of DC-DC converters need to increase. Higher frequencies require a design with lower parasitic inductance in order to minimize switching losses and to achieve acceptably high performance. As inductance is approximately proportional to the length of the wiring, the distances between devices must be minimized. Consequently, a multi-chip package design is required. Higher switching frequencies require smaller passive components, enabling savings in component cost and board space. Despite their increased manufacturing complexity, hybrid DC-DC converters therefore offer attractive benefits in performance and system cost. This paper presents how the characteristics of the PowerRibbonâ interconnect fit the requirements of such hybrid DC-DC converter multi-chip packages. Ribbon bonding capabilities critical to such applications are documented with examples from discrete small power packages, especially Power QFN packages. Starting with a layout compliant with the DrMOS package standard proposed by Intel Corp., lead frame design considerations with regards to a robust power interconnect process are discussed.
Christoph Luechinger, Director of Strategic Development
Orthodyne Electronics Corporation
Irvine, CA

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