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3-D Si Chip Stacking and Interconnection Process using Through-Si-Via
Keywords: three dimensional stack packaging, silicon chip stacking, SiO2
3-dimensional (3D) silicon chip stacking is a novel method to integrate chips for denser and smaller electronic components. Compared to conventional 2D integration in which chips are placed and connected in parallel way, the 3D chip stacking enables chips to be placed and connected in vertical way which provides shortest connection length and reduced volume of chip integration. In this study, to produce electrode embedded in Si chip, micro via were formed on Si chip by DRIE (Deep Ion Reactive etching) in which SF6 and C4F8 gas are provided alternately to etch Si. The produced through-Si-via was cylindrical shape having 40m in diameter and 70m in depth. Subsequently, 1m SiO2 layer was formed as insulation layer by CVD (Chemical Vapor Deposition), and 0.3m Ti and 0.5m Au layer was sputtered and deposited on SiO2 layer as adhesion and seed layer, respectively. Pulse current electroplating was used to make a Cu plugging in the via. After Cu plugging, Si wafer was back-grinded by CMP (Chemical Mechanical Polishing) until Cu plugging was exposed. Staking step was followed by reflow soldering process to interconnect Cu plug and Sn bump at 255C at ambient condition. By using the process developed, 5 layers-stacked module was produced successfully.
Wonjoong Kim,
University of Seoul
Seoul 130-743 ,
South Korea

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