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Delivering Cost Effective Wafer Level and 3D Packages with TSV
Keywords: TSV, Cost, Process
Chip scale packages fabricated on a wafer scale have front side interconnects. On attachment to a printed circuit board the active side of the package die therefore faces the substrate. This orientation is perfectly acceptable for die that have a purely electronic function. However for many types of RF devices, micro electro-mechanical systems and particularly image sensors and 3D packages the active face of the semiconductor must face away from the substrate, so it remains accessible after packaging and attachment to the next layer in the stack or to printed circuit board. To house a die, in a chip scale package fabricated at the wafer scale, in this orientation requires the bond pads on the die to be routed to the rear face of the semiconductor by through silicon vias. Through silicon vias have been technically achievable for many years, but have not been widely adopted by industry. The principal impediment is cost. Traditional through silicon via technology requires semiconductor-based infrastructure, tool sets and materials, making it a very expensive option suitable only for niche applications. There are also concerns about the reliability of many through silicon via implementations presented in the scientific literature. This paper will describe a through silicon via solution that was built from the ground up using the unconventional strategy where cost was the pre-eminent factor in the process design methodology. The final implementation can use low-grade infrastructure for many process steps, employs equipment from the printed circuit board industry and utilizes materials from the automotive industry. Process flow of wafer level of cost effective TSV for image sensors and stacked package utilizing the same TSV approach will be presented.
Moshe Kriman, VP Engineering
Jerusalem 96251,

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