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New 3D Interconnection Method by using Wet etching Technology
Keywords: stacking method, wafer to wafer, TSV
We have developed unique interconnecting technologies for 3D stacking devices with Through Silicon via (TSV). We demonstrated that the interconnections are shown very good connectivity and conductivities at last iMAPs conference. We fabricated 3D LSI devices with TSV/micro-bump interconnection using wafer-to-wafer staking technology. Each wafer was fabricated by using 0.18um CMOS technology based on 8-inch wafers. We showed that an electrical interconnection between each layer was almost 100% and less than 0.7 ohm. And then five prototype devices showed sophisticated functionality, and yield in the stacked wafer was over 60 %. Our stacking technology has two unique methods. One is Wafer-to-Wafer stacking method using a direct connection between backside TSVs of an upper wafer and micro-bumps of a lower wafer. This connection method is useful that all back-side processes are removed except wafer thinning, and also total stacking process is simplified and shortened. The other is that we used a wet etching technology as an additional wafer thinning process after a conventional back grinding process. The TSV stick out from the backside of the upper wafer by the wet etching. Therefore it is very important to optimize the wafer thickness for the good interconnection between each layer. We will show both the uniformity of the wafer thickness and the optimization of the backside TSV sticking out from the back-side of the upper wafer. And also, we have done some reliability test of Mil-std and JEDEC-std test. Moreover we will show the experimental results of an advanced TSV/micro-bump interconnection using our staking method.
Takanori Maebashi, Researcher
Honda Research Institute Japan
Wako, Saitama 351-0188,
Japan


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