Here is the abstract you requested from the DPC_2009_3D technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.
|High Insulating Through Silicon Via Integration in 200V SOI Applications|
|Keywords: Via first, polysilicon, high voltage|
|Connections between front and back sides of wafers with Through Silicon Vias (TSV) have been intensively developed during the last decade. Several options are possible, including via-first or via-last approaches. Via last was initially widely used in production for memory stacking or image sensors, with low resistivity copper used as the via filling material. However the via last technology is limited for high voltage applications, due to the temperature restrictions on the sidewall insulation. The via-first technique does not have this disadvantage since a good quality thermal oxide can be grown on the via sidewall before the process. In this case doped polysilicon is used for the via fill due to the very high subsequent thermal budget of semiconductor 200V SOI processes. Thermal oxide has the advantage of a very good electrical insulating FEOL material making TSV-first approach potentially interesting for high voltage 3D. We will present details of process development to achieve very high aspect ratio ring TSV in Silicon on Insulator (SOI) wafers using Reactive Ion Etching (RIE), with specific focus on the challenges of forming TSVs in SOI wafers. Oxide optimisation to achieve a good conformal layer with the best insulating properties and then filling with highly doped polysilicon are discussed. Specific test vehicle layouts were realised to characterize the quality of the process flow. Electrical test with daisy chains, pseudo Kelvins, and other structures to look at leakage and electrical breakdown will be presented. Breakdown voltages of up to 1KV between vias have been achieved. Comparisons will be presented between several structures with varying ring width and number, with or without a sacrificial ring, from the point of view of electrical, morphological, and process criteria.|
38054 GRENOBLE CEDEX 9,