Here is the abstract you requested from the DPC_2009_3D technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.
|The Evolution to 3D IC Integration|
|Keywords: 3D integration, 3D infrastructure, 3D processing|
|3D integration is happening because of a confluence of forces including portable device miniaturization and the end of CMOS shrinkage as we know it. 3D Integration entails vertical stacking of KGD or wafers using TSV, thinning and bonding technologies. There are currently a multitude of proposed 3D process flows out there for doing this. If one looks closely at the available infrastructure it is clear that some of these options will be much more suitable than others. This presentation will look at how the IDM, Fab and OSAT infrastructures are evolving towards 3D and which process & materials options look best suited to lead the evolution from 3D packaging (wirebonded stacked BGAs) to 3D Integration. I will also discuss the current roadblocks to widespread acceptance and propose a reasonable timing roadmap. I will also discuss the absurdity of the agressive market numbers being put out there by some of the market prognosticators.|
|Dr. Philip Garrou, Consultant
Microelectronics Consultants of NC