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Structural Design Aspects For Reliability of High-Density Chip-Scale Packages Using a Wafer-Stack Process
Keywords: WLCSP, Wafer Stacking, Thermal cycle reliability
Rapidly evolving video and image processing capabilities for next-generation electronic products have produced an insatiable demand for higher memory density for use in mobile devices such as phones and personal digital assistants (PDAs). The application space applies to both SD cards and embedded memory which are constrained by small form factors. This creates increased pressure on designers to develop packaging techniques that enable stacking of ultra-thin silicon dies in a small form factor. Each year, with the introduction of new stacking technology, the capacity gap between SD cards and ƒÝSD cards decreases. However, handling of very thin die in die-stacked packaging, and wafer stacking in the Through Silicon Via (TSV) process, presents unique technical and cost challenges which must be overcome in order to achieve high density packages. In this paper, a wafer-stack packaging approach is presented that circumvents the thin die/wafer handling issues and instead, uses cost-effective wafer-level processes such as interconnect joining and rerouting. Reliability is a crucial factor in qualification of this technology. The structural design features in the wafer-stack approach are analyzed for performance in regard to thermal cycling. Toward that goal, test results of finite element models of packages with up to sixteen stacked die are analyzed and reviewed for JEDEC standard JESD22-A104 specified thermal cycling tests. The thermal cycle reliability and failure modes are compared in a variety of material sets within the package with the goal of determining the most reliable package design. Results show that through design optimization and material selection, a reliable, high-density memory package can be achieved which addresses the needs of future memory applications. Keywords: WLCSP, wafer stacking, die stacking, finite element analysis, high density stacking, thermal cycle reliability, JESD22-A104.
Piyush Savalia, Mechanical Engineer
Tessera Inc.
San Jose, CA

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