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Critical Factors of Cu TSV Electrodeposition
Keywords: copper , electrodeposition, TSV
3D Interconnect using through silicon via (TSV) technology is currently believed to be the solution that can enable further progress and integration necessary for more advanced and superior electronic devices. There are different materials and methods that have been proposed and tested for TSV applications. Copper and electrochemical deposition processes have several characteristics that make them attractive for various semiconductor applications, including seed layer and TSV electrodes formation. Due to its applicability to a large variety of feature sizes and applications, in a more cost effective way than any other available techniques, copper electrodeposition has been identified as being the leading metallization approach to TSV. Initially it was believed that transfer of commercially available processes with proven manufacturability in printed wiring board (PWB) and copper damascene to TSV applications would be appropriate and very easily done. That was not the case; several factors were found to be critical for successfully implementation of such a technique, not just because of the larger variety of the structures that this technology is dealing with, however, especially because of the many integration challenges associated with various downstream processing steps that ultimately can have a significant impact on the performance of the electrochemical deposition step. To achieve reliable TSV structure, the quality of the seed layer is critical. When it comes to more challenging feature dimensions (aspect ratios of 5:1 and higher), traditional plasma vapor deposition (PVD) methods of seed deposition have been found not to be reliable enough to provide seed layers with good conformality and uniformity across the entire surface of the vias. More expensive ionized PVD systems are available today in the industry to overcome these limitations, however, at significantly higher processing costs. New seed layer deposition processes, such as seed layer enhancement (SLE) and direct on barrier deposition (DOB) have been developed to address these limitations in a more cost effective way. Advantages and applicability to different type of barriers and integration with the subsequent metallization process step will be presented. Other factors such as via profile, chemistry capabilities to wet high aspect ratio features and provide super-conformal deposition in addition to optimized process parameters were found to be critical in achieving the performance required for TSV applications. The effect of all these critical factors on performance, ease of applicability and cost will be presented.
Rozalia Beica, 3D Interconnect Director
Semitool
Kalispell, MT


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