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Evaluation of Seed Layer Coverage in High Aspect Ratio Trenches and Through Silicon Vias (TSV) using 300-mm Advanced Directional Sputtering (ADS)
Keywords: Through silicon vias, Seed layer, Advanced directional sputtering
Chip-to-chip vertical interconnection using Through Silicon Vias (TSV) enables three-dimensional microelectronic systems-in-package (SiP) with higher electrical performance and smaller size. TSV technology relies on Deep Reactive Ion Etching (DRIE) or laser drilling to create via-holes in Si substrates, PECVD of insulating layers and electroplating for via filling. Growing a conformal plated film requires a continuous seed layer (PVD or MOCVD), regardless of wall roughness (DRIE scallops) or sidewall profile (e.g., re-entrant profile). We report on the evaluation of Clusterline 300II Advanced Directional Sputtering (ADS) dedicated to seed layer deposition for 3-D packaging applications. Essential features of the developed PVD source are a modified long-throw process chamber and a high RF bias on chuck side. In particular, this paper describes the impact of via geometry by comparing two extreme designs: trenches and vias. Sputtering runs have been carried out on Si samples placed on 300-mm carrier wafers. The metal coverage in trenches and vias was characterized by measuring the amount of deposited Ti-Cu on different positions: top sidewall, middle sidewall and bottom center. Top sidewall corners without overhang and the presence of a dense and continuous Ti-Cu film on the middle and lower sidewall demonstrated the ADS suitability for 3-D packaging applications. The bottom coverage of trenches with AR=5 to 10 was 15%10%, whereas vias with AR=4 to 8 exhibited a bottom coverage of 4%1%. This database can be successfully employed for defining the top surface thickness that is necessary in order to provide an adequate seed layer for electroplating. A more detailed study of the ADS performance as a function of process parameters will be presented, including additional work on the film resistivity as a function of the ratio DC/RF bias power.
Patrick Carazzetti, Process Engineer
Oerlikon Systems
Balzers, FL 9470,

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