Here is the abstract you requested from the DPC_2009_3D technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.
|Chip embedding technology – New technological challenges for a reliable System-in-Package realization|
|Keywords: Embedded Chip Package, Hiding Dies / Chip in Polymer, 3D SiP|
|This paper intends to highlight the main technological achievements in the implementation of embedding technologies at development level and will show the main challenges for the successful further technology development towards a reliable packaging alternative at prototyping and industry level. Embedding of semiconductor chips into organic substrates allows a very high degree of miniaturization by stacking multiple layers of embedded components, superior electrical performance by short and geometrically well controlled interconnects as well as a homogeneous mechanical environment of the chips, resulting in good reliability. The outcome of the European project “HIDING DIES” on exploration of embedding technologies for advanced electronic systems will be presented. The embedding technology has used successfully lamination of Resin-Coated-Copper foils (RCC) and laser via interconnects to chip pads. The Hiding Dies project has successfully shown the great technological capabilities of chip embedding for miniaturized electronic systems and therefore has sparked tremendous interest for industrial adoption. As a result of the increasing interest in implementing embedding technologies in an industrial environment, a newly established European project “HERMES” will focus mainly on industrial adaptation of embedding technologies with an additional scope of improving also the existing technological capabilities at prototype level. At prototype level, the development focuses on the pad pitch reduction of the embedded silicon dies with the resulting fine pitch requirements for the chip contact and the fine line needs for the resulting wiring of the package. Different test vehicles, that realize QFN and stackable BGA packages, have been chosen to improve the technological capabilities. Results of the package realization and newly introduced technologies will be discussed. The use of a laser direct imaging (LDI) method in combination with semi additive copper deposition, that enables the patterning of lines and spaces down to 15µm and all the resulting challenges will be described in detail. The realized packages will be used for an extensive reliability testing according to standard package tests. The goal is to demonstrate reliability of the embedding technology. Results of these tests will be presented and discussed in depth.|
|Lars Boettcher, R&D Engineer
Fraunhofer IZM Berlin