Micross

Abstract Preview

Here is the abstract you requested from the DPC_2009_3D technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.

Photolithography in Vertical Vias for 3D TSV Application
Keywords: lithography, through silicon vias, vertical vias
3D integration using through silicon vias (3D TSV) is today’s emerging wafer level packaging (WLP) technology thanks to the high performance, systems integration availability and small package sizes. Image sensors packaging using TSV process is already in production, memory 3D stacking will follow soon. There are several strategies in manufacturing of 3D TSV: ranging form poly silicon vias in first steps of CMOS process, through manufacturing the vias after the finishing the FEOL up to completely separated silicon interposers. One of the approaches, often referred as “vias last after BEOL”, is process where TSV are created after thinning the wafer. In this process device wafer is flipped and bonded to the carrier wafer, thinned from the back side and TSV are etched. Afterwards the dielectric material is deposited. The purpose of dielectric layer is to insulate the via filling from silicon side walls – but the insulation should be open on via base to allow the electric contact between the via filling and metal pad on front side. One of the challenging processes, in this TSV strategy, is opening the insulator layer on the via base. This could be achieved, in some cases, by mask-less etching or generally by etching through resist mask. The requirements for resist mask are following: resist layer has to be conformal, all over the sidewall and edges, opening have to be well defined and cleared. It is extremely challenging for standard spray coating technology to achieve the conformal resist coating over today’s vertical high aspect ratio vias. Exposure in high proximity and development of resist in deep cavities pose another challenges. In this paper we will review the results of the exposure tests in vertical (90°) vias of various diameter and depth. Conformal coating will be presented as well as exposure results achieved by proximity lithography. Results of opening formation and lithography bias adjustment will be discussed.
Daniel Figura, Process Engineer
EV Group
St. Florian am Inn 4782,
Austria


CORPORATE PREMIER MEMBERS
  • Amkor
  • ASE
  • Canon
  • EMD Performance Materials
  • Honeywell
  • Indium
  • Kester
  • Kyocera America
  • Master Bond
  • Micro Systems Technologies
  • MRSI
  • NGK NTK
  • Palomar
  • Plexus
  • Promex
  • Qualcomm
  • Quik-Pak
  • Raytheon
  • Specialty Coating Systems