Here is the abstract you requested from the DPC_2009_3D technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.
|Thermal Management and Performance Optimization of 3-D Microelectronics System|
|Keywords: Thermal , Management, Packaging|
|The conjugate thermal performance of 3-D microelectronics system in a custom environment is evaluated and further optimized using numerical simulation and experimental validation. The industry deals with various package and module-level thermal issues when managing the routing of very high current. The study provides a better understanding of the strengths and weaknesses of the IC packaging incorporation into a system module level, for both present and future product development. The reference design is evaluated at a system level, and several improvements are identified to enhance the overall thermal performance. The main concern is the possibility of exceeding the thermal budget for the large system incorporating seven power packages with additional sources of heat dissipation in an enclosure, at an external ambient temperature of 85°C. The overall thermal impact of the metal trace dissipation, header heating and other passive components under various powered conditions is evaluated. An additional revised model includes additional passive components (32 LD SOIC and QFN packages) on the PCB. Several additional cases are investigated, varying the heat transfer coefficients outside the enclosure from 0 to 100 W/mK, while maintaining the ambient temperature at 85°C. The peak temperatures range from 121.4°C to 126.4°C and the corresponding junction-to-ambient thermal resistances (Rja) vary from 11.03°C/W to 12.5°C/W. The optimized numerical model approximates closely the empirical results (121-126C vs. 127.5C), within 1-2%.|
|Victor Chiriac, Principal Staff Engineer
Freescale Semiconductor Inc.