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Transient and Steady State Thermal Performance Evaluation of Stacked Die Designs in QFN Packages
Keywords: Stacked , Die , Thermal Management
The paper presents the thermal performance evaluation of a stacked die design in 5 x 5 QFN packages. The simulation accounts for conduction, convection and radiation in the 3-D system, and evaluates the design under transient as well as steady state operating conditions. The challenge resides in providing the appropriate thermal management solutions for localized hot spots on the Analog die, dealing as well with detrimental thermal interaction between the stacked MCU and Analog die at a high ambient temperature of 85C. The small NMOS and PMOS FETs (micron range) dissipate localized heat, and the challenge is to conduct the heat away from the local hot spots to the bottom heatsink (PCB) while the MCU die dissipates additional heat acting as a thermal barrier to the heat in the Analog die. Several designs are evaluated, while varying the PCB size, the power dissipated in the FETs as well as the active area structure on the Analog die. The transient study reveals the optimal signal duration in order to satisfy the thermal budget and keep the device in optimal operating conditions. The peak temperatures range from 117C to 180C depending on the operating conditions. The best thermal performance designs are identified and further discussed.
Victor Chiriac, Principal Staff Engineer
Freescale Semiconductor Inc.
Tempe, AZ

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