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Achieving Higher Efficiency in Complex IC Package/SiP Design through 3D DFM Integration with Manufacturing Systems
Keywords: Wirebonding, DFM, 3D
Todays leading edge devices demand maximum functional density and performance in the smallest, lightest and lowest cost package. The majority of todays IC Package designs still use the wirebond attachment methodology, and if die stacking is being utilized to increase overall device functional density/capacity then wirebond attach is the only cost effective proven methodology to use. However, when designing with wirebond attach a level of 3D geometric complexity is introduced that usually prevents the designer from being able to optimize for the manufacturing process. This can lead to an un-optimized design that either is not manufacturable or does not meet the design specifications. This process is further complicated by the sophistication and capability of todays state-of-the-art wirebonding equipment. In such design scenarios, the manufacturing engineer may be forced to perform multiple wirebond simulations and prototype runs in order to achieve manufacturing viability which results in production delays. In a worst case scenario, the manufacturing engineer may need to throw the design back over the wall to the design engineer for modification. This paper will highlight what todays state-of-the-art wirebond assembly tools are capable of, how todays design tools can be enhanced to be more DFM capable/aware and finally what level of DFM knowledge/IP can be communicated within the design/supply chain to reduce/remove todays yield and design re-spin risks.
Keith Felton, Product Marketing
Cadence Design Systems Inc.
Chelmsford, MA


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