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Cost Effective Approach to 3D Integration with iTSV
Keywords: TSV, 3D, CoO
The development of IC technology is driven by the need to increase performance and functionality while reducing size, power and cost. The continuous pressure to meet those requirements has created innovative, small, cost-effective 3-D packaging technologies. General advantages of 3-D packaging include the miniaturization of size and weight, the integration of heterogeneous technologies in a single package, the replacement of long 2-D interconnects with short vertical interconnects, and the reduction of parasitics and power consumption. Therefore, 3-D packaging can offer significant advantages in performance, functionality and form factor for future technologies. Until now, and for the near future, the typical trend in technology development is to move from 2-D configuration to 3-D stacking (with wires, bumps and micro vias), and then move to 3-D ICs with TSV interconnects in order to reduce footprints, increase silicon efficiency, and have shorter interconnects. Today, wire bonding is limited in terms of density and performance, and flip-chip cannot be broadly adopted for chip stacking. Therefore, TSV technology seems to be unavoidable in the near future for miniaturization first and then performance improvement. As far as markets and devices for 3-D ICs are concerned, flash memories, image sensors and heterogeneous stacking (memories plus logic) are the major targets, where image sensors and flash memories are two mass volume applications for pTSVs with near volume production today. There are various kinds of 3-D packages based on stacking methods, which include on-chip 3-D integration based on layer-by-layer build-up of functional layers within a chip; 3-D stacking with die-to-die stacking or package-to-package stacking (package-on-package [POP] or package-in-package [PIP]); and 3-D ICs (3-D integration of ICs), which have die-to-die interconnection with through-silicon vias (iTSVs). Among all kinds of 3-D packaging techniques, TSV electrodes can provide the shortest and most plentiful Z-axis connections. Move to 3D from WLCSP per Beth Keser and Andy Strandjord 12-10-08.
Paul Siblerud, VP WLP SEMITOOL
EMC3D
Kalispell, MT


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