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The Solution of Crack Issue at Boundary Surface between FC (Flip Chip) Substrate and Underfill in Various Semiconductor Packaging Conditions
Keywords: FC (Flip Chip) substrate, Packaging, Reliability
In semiconductor packaging process, chip assembly companies use their own process condition. Depending on the packaging process conditions, various stresses are applied on both chip and substrate. The crack issue at boundary surface between FC (Flip Chip) substrate and underfill is often occurred after package reliability test (ex. HAST, TC/B, and so on). In order to avoid this, substrate properties should be improved for the various packaging process. We found the root cause and proposed mechanism of the crack through experiments. This paper shows the solution for the package reliability problem in various assembly conditions.
Cheol-Ho Choi, Principal Engineer/ Program Manager
Samsung Electro-Mechanics
Pusan 618-721,
South Korea


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