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Chip Joining of High End Flip Chip Organic Packages - Interconnect Pitch Reduction Challenges
Keywords: flip chip, fine pitch, organic
As the semiconductor technology nodes move to 45nm, 32nm and then 22nm, the question of fundamental limits to traditional transistor scaling becomes increasingly prevalent. Does this same concern transcend to the chip to substrate interconnect? With each node, and its corresponding increase in transistor density, interconnection density from chip to substrate must increase accordingly, hence driving down the size of each interconnection. On the other hand, the drive to designing more performance into each semiconductor device results in other aspects of the device that do not scale accordingly; for example current density per interconnection and chip size. Moreover, material sets are not standing still - more fragile low K dielectrics, Pb-free solders and denser, more complex organic substrates all impose additional challenges to the chip-substrate interconnection. So it becomes incumbent upon those tasked with designing, manufacturing, and assuring the quality of packages with higher numbers of finer pitch/smaller interconnects to first determine the pinch points then explore innovations in either material sets or processes to best address such pinch points. This paper focuses upon the pinch points that finer pitch interconnections impose specifically upon the flip chip solder reflow join process. The role of this process is to not only form reliable solder joints between chip and substrate but to do so in a manner that does not adversely affect the integrity of isolation between interconnects nor the integrity of the semiconductor device itself. As such, challenges in these areas associated with joining large chips to organic substrates using 150 pitch solder interconnections, both in Pb containing and Pb-free compositions will be examined in detail. Fundamental geometrical limitations related to wetting area, CTE mismatch and substrate co planarity as well as the impact of the distribution of these geometries, will be discussed. The roles of interconnect alloy composition and chip BEOL dielectric fragility shall be explored. The inter-relationships between these issues and processing parameters such as chip placement, fluxing, reflow profiles and cleaning will also be addressed. Finally, the aforementioned issues and relationships will be looked at from the perspective of moving forward to 125, 100 or 50 pitches.
David Danovitch, Senior Engineer
IBM Canada Ltd.

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