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Polymer-Based Wafer Bonding Technology for MEMS Applications
Keywords: adhesive wafer bonding, wafer level packaging, polymer wafer bonding
IC performance is drastically limited by line-to-line capacity coupling and RC interconnect delay times resulted from the continuous increase in integration densities with 0.10m line and space width approaches, as well from increased signal frequencies. The new achievements in terms of circuit lines shrinkage emphasize the need for the introduction of Cu and low-k dielectric materials The main properties of the dielectric materials required for a large field of versatile applications/designs can be summarized in: isotropic dielectric constants, good thermal stability, low CTE and a good adhesion to different substrates. Commercially available polymer dielectric materials, like SINR series from Shin-Etsu MicroSi can fulfill these demands. The new materials not only opened new application areas, but also penetrated well established technologies. The extensive field of polymer-based applications ranges from interlayer dielectric applications - chip stacking by vertical 3D interconnections, to device encapsulation. These technologies realized in vertical interconnection and wafer-level packaging (WLP), are viable solutions for increasing electronic device functional density and reducing total packaging costs. This paper reports on wafer-to-wafer adhesive bonding using SINR polymers. Substrate coating process as well as wafer bonding process parameters optimization was studied.
V. Dragoi, Chief Scientist
EV Group
St. Florian, Upper Austria 4782,
Austria


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