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System Level Thermal Performance Optimization of Wafer Level CSP Designs
Keywords: Thermal , Simulation/Optimization, WL-CSP
A detailed numerical study was performed to examine the thermal performance of various WL-CSP designs at the system level under various ambient and powering conditions. Several system level variables are investigated, including the solder ball array structure, PCB thermal via distribution, die size, local versus uniform power dissipation under JEDEC and critical custom operating conditions. The thermal performance challenges encountered by the WL-CSP reside in the appropriate combination of the solder balls design coupled with the thermal via array structure in the PCB, particularly for localized die hot spots. The device performance is sensitive to the board that it is mounted on, as 98% of the heat is conducting into the PCB. Another challenge addressed by the study is to determine the maximum current carrying capabilities for a given RDL trace configuration and associated solder ball structure, especially for high current pins. The study uses extensive conjugate heat transfer techniques (conduction-convection-radiation) to evaluate several designs while varying the die size, the power dissipation as well as thermal via structures. At 25C ambient and discrete power with four thermal vias, the junction to ambient thermal resistance Rja reaches 77.2C/W, validated against previous experimental measurements. For the design with uniform power dissipation and 4 thermal vias, the Rja resistance drops to 67C/W. Finally, for the case with uniform power and full via array, Rja reaches 45.4C/W. Several additional studies identify the optimal thermal WL-CSP design.
Victor Chiriac, Principal Staff Engineer
Freescale Semiconductor Inc.
Tempe, AZ


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