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Lithographic Process Optimization Of a Low Temperature Curable Epoxy-Based Dielectricfor Wafer Level Advanced Packaging
Keywords: low temperature cure epoxy dielectric, photolithographic characterization, braodband stepper exposure
Advanced Packaging of semiconductor devices is a major area of development and growth in both the “front-end” wafer fabs as well as the “back-end” assembly operations. New processes and associated materials are being continually designed to improve form factor, price and performance of the packaged devices. Dielectric materials are a key component of advanced packaging, enabling applications such as stress buffer coat, bond pad redistribution for solder bumping and wafer fan-out/embedded components (FoP/ eWLB). Emerging uses of these dielectrics are in 3D-IC processes such as permanent wafer to wafer bonding and Through Silicon Via (TSV) metal isolation and via fill. This study will focus on the performance of a commercially available, negative acting, aqueous developable epoxy dielectric, applied at a film thickness with feature dimensions (CD) that are commonly used for FoP applications. It is advantageous for the dielectric material to utilize common equipment sets previously used for BEOL operations in the fabs. Therefore, a broadband stepper with a mercury lamp spectrum from 350 nm to 450 nm (g,h and i-line) is utilized to expose the photosensitive epoxy material. This tool has been optimized for thick photoresists and dielectrics and uses a combination of low numerical aperture and high wafer plane intensity to achieve well formed images in thick films. Process capability for 200 mm wafers is determined by analyzing film thickness uniformity and CD control across the wafer. Basic photoresist characterization techniques such as cross sectional SEM analysis, process linearity and process windows are also used to establish lithographic capabilities. Since these polymeric dielectrics become a permanent part of the packaged device, their thermal, electrical and mechanical properties will be discussed in addition to their photolithographic characterization. The trade-offs for various process capability windows are reviewed to determine the optimum process conditions for different advanced packaging dielectric applications.
Eric Huenger, Senior Advanced Packaging Engineer
Rohm and Haas Electronic Materials
Freeport, NY


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