Here is the abstract you requested from the DPC_2009_Wafer technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.
|Solder Brace Coatings for Wafer-Level Chip Scale Packaging|
|Keywords: wafer level adhesive, solder bracing, wafer level underfill|
|For wafer-level chip scale packages (WLCSP), board level solder joint reliability is a major concern, and typical stress-relieving methods such as capillary underfills and molding compounds are costly. One method of low cost reliability improvement for WLCSPs is the use of a wafer level solder brace coating, which delivers improved reliability with minimal material and capital cost. In this presentation, the process of using a highly filled, photo-definable coating will be discussed. Spin-coat application of the material onto wafers forms a photo-definable polymer layer that reinforces the solder joints. Processing of the solder brace coating is similar to that of polyimides: spin coat, bake, photo-image, solvent develop, and cure. Unlike polyimides, these coatings are low temperature cured, have low CTE values (18-20ppm), and have minimal wafer warpage. These properties make a solder brace coating attractive as an alternate passivation coating, while also functioning as a partial underfill. Partial underfills are known to offer improvements in thermal cycling and drop reliability. Solder brace coatings are thermally, mechanically, and chemically robust, offering a unique method to package low cost high performance WLCSPs.|
|Candice Brannen, Senior Scientist