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|Amkor’s CSPnl™: Comparison of Bump on Pad and Cu Redistribution WLCSP Designs|
|Keywords: WLCSP, CSPnl, Amkor|
|Amkor’s CSPnl™ (Chip Scale Package-next level) includes a Bump on Pad (BOP) WLCSP and a fan-in design with a Copper redistribution layer (RDL) for conversion of wire bond devices to WLCSP. Understanding influences on reliability for design differences between BOP and Cu-RDL stackup is crucial to increasing device lifetimes and expanding the application space for WLCSP. Amkor uses board level reliability (BLR) testing with extensive failure analysis which is integrated with computer modeling to characterize failures. Identification of failure initiation points and mechanisms for failure drive improvements in design and in turn, WLCSP performance. This paper will provide an update on Amkor’s latest BLR results for CSPnl™ of both BOP and RDL designs and a comparison of the failures in each package structure. The reliability results include drop impact and thermal cycling stress testing as governed by the JEDEC standards JESD22-B111-B and JESD22-A104-C, respectively. Package design parameters that were varied include, but are not limited to, dielectric thickness, solder type, and Cu thickness. In addition, the paper will include a short discussion on the corresponding computer modeling (ANSYS Mechanical/ LS-DYNA) used to explain failure modes. The simulation discussion will cover static mechanical deformation for drop and thermal stress for temperature cycling.|
|R. Anderson, Manager II-Development