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|Thermal Reliability Performance of Large Area WLCSP Arrays|
|Keywords: WLCSP, RDL, Thermal Shock|
|WLCSP technology is being rapidly adopted as the package technology of choice for ICs in portable personal electronic products. Recently, nanometer scale CMOS products have utilized area array WLCSP packaging for both performance and cost reasons. However, selection of appropriate WLCSP technology and its optimization are necessary to build reliable products. Nanometer scale CMOS technology has multiple levels of metal layers, separated by low temperature deposited oxide layers, as interconnects. This fragile interconnect structure is susceptible to delamination, cracks, and even physical rupture induced by thermo-mechanical stress during routine thermal reliability testing such as thermal shock and temperature cycling. In this paper, we discuss the physical damage created in the inter-metal oxides and metal layers during thermal reliability testing of CSP arrays. ICs manufactured using conventional 180 nm CMOS are packaged using 0.5mm pitch WLCSP technology. The devices are assembled on a FR4 board and then tested for functionality. Subsequently, the devices, mounted on the board, are subjected to thermal shock from -40C to 85C. Several devices exhibit functional electrical failure after thermal shock. Detailed physical analysis performed on failed samples reveals severe delamination of various inter-metal layers and rupture of the interconnect network. Cracks are observed in the inter-metal oxide layers around the periphery of failed solder balls. Predominant failure is observed around the edge and corner balls. Use of underfill during board assembly reduces the failure dramatically. We also find that Redistribution Layer WLCSP (RDL-WLCSP) process results in improved thermal reliability even without the use of underfill. The thermal performance of the RDL-WLCSP process can be further improved by tailoring the thickness of various UBM and polyimide layers. To understand the failure mechanism, we construct a finite element model (FEA) of the IC packaged as a (10 x 10) area array and mounted on a FR4 board. Simulation results agree with experiments, confirming our hypothesis and validating the model. The model is also successful in explaining the reliability improvements that result with either the RDL-WLCSP process or addition of underfill to the conventional WLCSP process.|
|Umesh Sharma, Director, Foundry Operations
California Micro Devices