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A Test Platform for the Thermal, Electrical, and Mechanical Characterization of Packages
Keywords: thermal test chip, MCM reliability, package characterization
High performance microprocessors have demanding thermal and electrical requirements and require increasingly complex packages, such as multi-chip modules (MCMs). New package technologies must be characterized to ensure they can dissipate sufficient amounts of heat, deliver clean power, and reliably maintain mechanical tolerance. In this paper we present a test platform capable of characterizing a package's static and dynamic performance with fine spatial and temporal resolution. The test platform targets new MCM packages using Proximity Communication to enable 3D integration.

We fabricated a chip implementing the test platform in a TSMC 180nm, 1.8V process. The chip measures 15mm x 12.5mm and is bonded to a 40mm x 40mm, 894-pin, ceramic BGA flip chip package. The test chip contains a grid of 3944 unit cells, each containing heaters, a CMOS thermometer, and static VDD and GND measurement circuits. The heaters are MOSFET devices allowing an individually programmable power draw for a theoretical maximum of 355W at 1.8V. Each unit cell measures 180um x 180um giving finer static measurement resolution than in other thermal test chips in the literature.

The chip supports profiles and measurement capabilities to emulate dynamic power scenarios. This is accomplished by storing four power settings in each unit cell, which are cycled at up to 1GHz. Nine VDD samplers distributed across the test chip measure the resulting power supply transients. These samplers are able to sample power supply transients into the tens of GHz and voltages from 1.6V to 2.2V.

The ability to align chips under thermal cycles and mechanical loads also determines package reliability. Nine evenly distributed measurement structures determine chip-to-package separation with micron-scale accuracy. Also, because MCMs using Proximity Communication must align multiple chips precisely, eight sensors around the chip's perimeter determine alignment to a neighboring chip in six degrees of freedom.

Justin Schauer,
Sun Microsystems
Menlo Park, CA

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