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High Accuracy Placement Enabling High Density and Fine Pitch in 3D-IC with High Density TSV, with Chip to Wafer (C2W) Bonding Approach
Keywords: 3D-IC, Flip Chip, Chip to Wafer
With the advent of 3D-IC and the increased Packaging density, the introduction of Through Silicon Via technology and the associated High Accuracy Placement and Bonding Challenges introduce new requirements to make Chip to Wafer population a reality. It becomes even more critical when Chip Sizes increase while the Bumps dimensions or the TSV pitches decrease. The paper describes the know how acquired in Bonding High End Infrared Imager, either with In-Situ Reflow or Thermo-Compression Techniques which are compatible with interconnection metal-to-metal or with creation of inter metallic (i.e. Cu-Cu, CuSn). The Thermo-Compression will be illustrated by a technique of micro insertion into indium for an imager application.
Gilbert Lecarpentier, Product Manager
Saint Jeoire 74490,

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