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Flip Chip Process using the Cu-Sn-Cu Double-Pillar-Bump Bonding
Keywords: flip chip, pillar bump, RF-SOP
RF packages utilizing millimeter wave have drawn much attention to realize high speed communication systems, automotive radar, and high resolution medical imaging systems. System-on-package(SOP) has advantages of size reduction and high electrical performance due to high integration of IC chips and passive components in a single package. In RF-SOP, IC chips are mounted on the substrate by flip chip process. While bump size and pitch of IC chips decrease substantially, the gap distance between the chip and substrate should not be reduced so much to prevent deterioration of electrical characteristics of the RF-SOP. In this study, a flip chip process using Cu-Sn-Cu double-pillar-bump bonding has been investigated for RF-SOP applications. Cu pillars and Sn sandwich layers were formed by electrodeposition and flip-chip bonded to form the Cu-Sn-Cu double-pillar-bump joints. Microstructures of the joints were observed using SEM. Contact resistances and chip shear forces of the flip-chip specimens were measured as a function of the sandwiched Sn layer thickness. Thermal cycling reliability and high temperature storage characteristics of the Cu-Sn-Cu double-pillar-bump joints were also evaluated.
Tae-Sung Oh, Professor
Hongik University
Seoul 121-791,
Korea


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